Apparatus and method for optimizing performance of a cache memory in a data processing system
US5375216A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 1992 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Feb 28, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.