Method of fabrication of adjacent coplanar semiconductor devices
US5376229A · kind A · utility
6Cited by
3References
13Claims
0Family size
Inventors
Key dates
| Filing date | Oct 5, 1993 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Oct 5, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02546
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing coplanar semiconductor devices of different types as provided. The method includes the steps of: forming a first layer for formation of a first device region on a substrate, forming an epitaxial semiconductor lift-off layer above the first device region, removing a portion of the first device region to open areas for the formation of the second device region, depositing epitaxially a second device region, and removing the liftoff layer to leave the first and second device regions remaining on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.