High-speed complementary multiplexer
US5376829A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1993 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Sep 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The complementary multiplexer includes a first pass-gate, formed from a single PMOS transistor, and a second pass-gate formed from a single NMOS transistor. The gates of the PMOS and NMOS transistors are connected directly to a select input line. No inversion of the select input signal is required. A compensation circuit is connected to outputs of the pass-gates for compensating any voltage differences between signals received through the first pass-gate as opposed to those received through the second pass-gate. Full CMOS and bi-CMOS implementations are described herein. An exclusive OR-gate circuit, incorporating a bi-CMOS implementation of the multiplexer, is also described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.