Delay matching circuit
US5376848A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1993 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Apr 5, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00117
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements. The disclosed delay matching circuit is useful in circuits, such as phase locked loops, where the simultaneous propagation of two signals is critical.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.