Absolute value comparing apparatus for comparing absolute values of data at high speed
US5376915A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1993 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Apr 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an absolute value comparator for comparing respective absolute values of sequentially applied two data. A decoder circuit sequentially converts the applied data into a plurality of bit signals in accordance with a predetermined rule. After a preceding conversion bit signal is once held in a register circuit, the held bit signal is inverted for each bit by an inversion circuit. Thus, a logic circuit receives a preceding inverted bit signal and a succeeding conversion bit signal and outputs an output signal B indicating the result of comparison. Since a full adder is unnecessary, a comparison between the absolute values of the applied data can be made at a high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.