One-bit switched-capacitor D/A circuit with continuous time linearity
US5376936A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1993 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Jun 16, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A modified lossy integrator digital-to-analog converter includes an amplifier (46) that receives an input on a summing node (48) and provides an output on a node (52). A feedback capacitor (50) is disposed across the input and output and has an output switched-capacitor (54) disposed in parallel therewith to passively distribute the charge thereacross. Switches (60) and (66) are operable to control the switching operation of the capacitor (54). Two input switched capacitors (70) and (94) are controlled by associated switches to switch charge onto the summing node (48) in a first clock cycle .phi..sub.2. A one-bit data stream modulates the operation such that either the charge from the capacitor (78) is dumped onto the summing node (48) or the charge from the capacitor (94) is dumped onto the summing node (48). This operation during the .phi..sub.2 cycle provides an integrated output that is slew-limited. The full charge of the selected capacitor (78) or (94) is allowed to be completely dumped onto the node (48) prior to the output switched capacitor (54) being disposed across the feedback capacitor (50). This allows for a linear operation in this range. Thereafter, the charge is pa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.