Hierarchical redundancy scheme for high density monolithic memories
US5377146A · kind A · utility
54Cited by
5References
7Claims
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Key dates
| Filing date | Jul 23, 1993 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Jul 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hierarchical redundancy is implemented in a monolithic memory by providing standard row and column redundancy augmented by redundant blocks, each having its own internal row and block redundancy. The efficiency of the redundant blocks is further enhanced by subdividing the redundant blocks into individually replaceable segments of rows or columns. A test and repair algorithm utilizing the hierarchical redundancy scheme is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.