Fault tolerant clock with synchronized reset
US5377205A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 15, 1993 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Apr 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant clock system that includes voting of power-on and other reset signals to ensure tight synchronization. A fault tolerant clock system (10) includes four channels, providing tolerance to a catastrophic failure in one of the channels and a second fault in another channel. Each clock channel comprises a crystal oscillator (12), an RC circuit (14), and a gain circuit (16) that are connected in a feedback loop with a first voter module (18). The first voter module produces a voted time base output signal corresponding to a majority vote of the timing signals provided by each of the four clock channels. This voted time base signal is fed back to the crystal oscillator through the RC circuit. The RC circuit enhances the frequency pulling capability of the crystal oscillator, enabling its timing signal to be phase shifted over a relatively wide range so that it can be kept in phase and frequency synchronization with the timing signals from crystal oscillators in the other clock channels without need for critically trimming components. A second voter module (34) determines a majority vote of reset signals from each of the clock channels, and the voted reset signal is applied…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.