Fractionally-spaced equalizer for a DS-CDMA system
US5377226A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 1993 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Oct 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03509
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An adaptively-tuned filter (80) for use within the receiver (14) of a multiple-access code division (CDMA) communication system permits spectrally-inefficient transmissions to be made from each transmitter (12) used with such system, thereby simplifying the transmitter circuits, yet still achieves a signal-to-noise ratio (SNR) that approaches the SNR achieved when spectrally-efficient transmissions are made. The adaptive filter (80) also compensates for signal distortions resulting from multiple signal paths. The receiver (14) includes RF receiving circuits (60, 62), a matched filter (64), downconversion circuits (66, 68, 92), sampling circuits (70, 71, 72), a time acquisition circuit (76), an adaptive filter (80), a decimator circuit (75), a despreader circuit (77), and an accumulator circuit (78). The adaptive filter (80) includes, e.g., two LMS gradient filters (96a, 96b), or equivalent, that operate independently in parallel, with an accurate bit decision being used to select the tap signals to be used as the starting point for the next bit. The filters (80, 96) function as a fractionally-spaced chip-MSE equalizer that improves the bit-SNR in the presence of sufficient multi-ac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.