Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system
US5377345A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1994 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Apr 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the CPU and a cache controller (CC), and is subblocked to reduce miss rate. The CC is coupled via a high speed bus to a main memory. A cache directory in the CC tracks usage of the external cache, and is organized to support a choice of bus protocols for buses intercoupling the CC to the main memory. The cache directory consists of tag entries, each tag entry having an address field and multiple status bit fields, one status bit field for each subblock. The status bit fields, in addition to shared-, owner-, and valid-bits, have a pending-bit which, when set, indicates a pending uncompleted outstanding operation on a subblock, and will prevent the CPU from overwriting the corresponding subblock. Two block miss registers in the CPU aid in prefetching subsequent subblocks upon subblock miss. The block miss registers further identify operations known to be pending but not particularly identified by the set pending-bit. One block miss regis…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.