Method and improved apparatus for stabilizing analog-to-digital circuits
US5379039A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1993 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Jul 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/43
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital (A/D) circuit comprising a multi-pole gain stage, a quantizer, and a feedback stage is stabilized when an analog input signal is excessive in the following manner. A stabilization detector continually samples a representation of stabilization of the A/D circuit. When the representation of stabilization is unfavorable, the stabilization detector increases, via a stabilizer, phase margin by adjusting the pole locations of the multi-pole gain stage based on the degree of unfavorability of the representation of stabilization. With the increased phase margin, the A/D circuit continues to provide digital representations of the analog input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.