Method and apparatus for simulating a microelectric interconnect circuit
US5379231A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1992 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | May 29, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for simulating a microelectronic circuit or system includes the storing of a microelectronic circuit or system representation in a computer and then transforming the representation into an equivalent DC circuit containing resistive, capacitive and inductive elements. Then, a directed graph of the DC equivalent circuit is generated and a spanning tree is constructed therefrom. The spanning tree is then actually or virtually traversed to obtain multiple generations of circuit moments. The moments are then used to calculate the poles and residues for a given node and generate an approximate model of the circuit's transient response at that node. Moment shifting is used to provide for a stable approximate model. The actual residues corresponding to the coefficients of the time domain representation for the model can be calculated using the first q-1 moments. This constitutes a partial-Pade approximation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.