Method and apparatus for static RAM
US5379251A · kind A · utility
9Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 1993 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | May 13, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
An SRAM memory cell structure, wherein a word line is disposed near the center of a cell, each one of driver transistors is disposed on both sides thereof substantially in parallel with each other, a contact portion for a gate electrode of said driver transistor is formed being laminated on a word transistor formed together with said word line, and a semiconductor, wherein an upper transistor and a lower transistor are disposed, an overlapped portion in which at least three layers each having a diffusion region for forming each of said transistors are overlapped is formed, and a contact is taken at said overlapped portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.