ECL test access port with low power control

US5379302A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventor

• John R. Andrews · Fairport, US

Key dates

• Filing date: Apr 2, 1993
• Grant date: Jan 3, 1995
• Expiry date: Apr 2, 2013

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318575
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit device ECL test access port (TAP) is constructed for low static current requirements and low power consumption when the TAP is inactive. The ECL test access port may conform with IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. An SCS logic circuit (50) is incorporated in the TAP controller coupled to the flip-flops (32,34,36,38) of the TAP controller n state finite machine for generating a current sink switch control signal (SCS) according to the state of the TAP controller. A current sink switch circuit (24) is coupled to respective current sinks of ECL gates incorporated in the boundary scan register (BSR/TDR1), design specific TAP data registers (DS/TDRs), TAP instruction register (TIR), and device identification register (DIR/TDR3). The current sink switch circuit (24) has an input coupled to the SCS logic circuit (50) to receive the current sink switch control signal (SCS). The current sink switch circuit is constructed to turn off the respective current sinks (Q4/R5, Q5/R6, Q6/R7) of the selected TAP registers in response to an SCS signal having a first logic value to reduce power dissipation when the TAP controller is in the inacti…