Configuration data loopback in a bus bridge circuit
US5379384A · kind A · utility
90Cited by
5References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1993 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Sep 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing cost and complexity of devices in a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back "bridged" configuration data to access configuration registers. The host bridge circuit "bridges" all I/O accesses received over a host bus directly to a peripheral component bus without any decoding. The CDC is both initiator and target on the peripheral component bus for I/O access cycles generated by the host bridge circuit that are targeted for a host bridge configuration register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.