Write ordering for microprocessor depending on cache hit and write buffer content
US5379396A · kind A · utility
16Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1991 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Oct 11, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.