Apparatus and method for managing interrupts in a multiprocessor system
US5379434A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 1994 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Jun 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for selecting a processor to service interrupts in a multiprocessor system with processor individualized interrupt priority states. The interrupt priority information associated with the various processors is bit serially compared to select one or more processors of lowest interrupt priority status, Processor individualized identification information is then compared to reconcile when multiple processors have an identical interrupt priority level, The outcome is stored and immediately available for managing interrupts generated by I/O devices, In a preferred arrangement, the interrupt priority status of the selected processor is confirmed immediately before processing the service requests to compensate for any changes occurring during the period of the bit serial comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.