Parallel processor with array of clustered processing elements having inputs seperate from outputs and outputs limited to a maximum of two per dimension
US5379440A · kind A · utility
30Cited by
15References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 17, 1991 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Dec 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is provided (FIG. 1) comprising a plurality of processing elements (10) arranged into D dimensions and divided into clusters (11), wherein all elements in a cluster have a bus (13) for communicating therebetween. Each element is a member of one cluster in each dimension. Each element in a cluster is connected to the bus in that cluster by output means (FIG. 3), for sending messages to a plurality of other elements in the cluster, and separate input means corresponding to each other element in the cluster for receiving messages from each other element on the corresponding separate input means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.