ECL gate having active pull-down transistor
US5381057A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 3, 1993 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | May 3, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0136
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a modified emitter coupled logic circuit which includes a differential logic stage and an emitter-follower output stage. An active pull-down circuit and a constant voltage source are included in the output stage of this circuit to allow the output of the circuit to switch from a high level to a low level at approximately the same speed as the output can switch from a low level to a high level. A particular embodiment of the present invention provides a constant voltage source comprising an operational amplifier, a reference potential generating circuit and a constant voltage signal adjusting circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.