Efficient functional test scheme incorporated in a programmable duration binary counter
US5381453A · kind A · utility
9Cited by
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32Claims
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Inventor
Key dates
| Filing date | Feb 9, 1994 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Feb 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A new technique for testing the counting functionality, loading functionality, and operational speed of a binary counter is provided wherein additional logic is incorporated into the counter to enable the counter to be functionally tested with a minimum number of clock cycles. Thus, for an n-bit counter which is partitionable into k subcounters, the counting functionality and operational speed of the counter may be tested in at most 2.sup.n/k +2 clock cycles, and the loading functionality of the counter may be tested in at most 2.sup.n/k +1 clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.