Patent · US Expired

Interface: interrupt masking with logical sum and product options

US5381540A · kind A · utility

21Cited by

8References

20Claims

0Family size

Assignee

Dallas Semiconductor Corporation · US

Inventors

Matthew K. Adams · Dallas, US
Wendell L. Little · Carrollton, US
Stephen N. Grider · Corinth, US

Key dates

Filing date	Dec 2, 1992
Grant date	Jan 10, 1995
Priority date	—
Expiry date	Dec 2, 2012

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/26
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR. The circuitry also comprises a mask register having a plurality of mask register inputs and a plurality of mask register outputs, the plurality of mask register inputs connected to the plurality of interrupt inputs and the plurality of mask register outputs connected to the plurality of combinatorial logic inputs wherein a mask register bit pattern in the mask register conditions a corresponding subset (possibly empty) of the interrupt signals at the plurality of interrupt inputs to make the function and the…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.