Programmable system for prioritizing and collecting central processor unit interrupts
US5381552A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1993 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Apr 26, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A priority selector prioritizes interrupts associated with each ASIC of a plural ASIC system in accordance with a programmed sequence. A table in each ASIC contains a programmable offset table and a programmable priority code table. The table selects an offset value and a priority code associated with the highest priority interrupt for the ASIC. An interrupt collector includes a priority compare to identify the priority code of the highest-priority interrupt of all of the ASICs. A multiplexer selects the offset value associated with it. The offset value forms a jump or offset address to the interrupt for the CPU. The priority sequencing, offset tables, priority code tables and priority compare values are programmable, so the prioritizing is adjustable. Each priority selector generates an interrupt active signal for the CPU. A mask disables interrupts until serviced by the CPU so that any interrupt active signal resulting from a disabled interrupt is terminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.