Method for forming MOS transistors having vertical current flow and resulting structure

US5382538A · kind A · utility

Assignees

• Consorzio Per la Ricerca Sulla Microelettronica · IT
• SGS-Thomson Microelectronics S.A. · IT

Inventors

• Raffaele Zambrano · Catania, IT
• Carmelo Magro · Catania, IT

Key dates

• Filing date: May 21, 1993
• Grant date: Jan 17, 1995
• Expiry date: May 21, 2013

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/126

Abstract

The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.