Semiconductor device and method of fabricating same, as well as lead frame used therein and method of fabricating same
US5382546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1993 |
| Grant date | Jan 17, 1995 |
| Priority date | — |
| Expiry date | Nov 10, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device having a number of pins, there is used an inner lead group comprising a group of upper inner leads 7A present in an upper plane and a group of lower inner leads 7B in a lower plane, the upper inner lead group and the lower inner lead group being laminated together in an insulated from each other through an insulating layer 2C, both end portions in the circumferential direction of each upper inner lead 7A being overlapped with circumferential ends of adjacent lower inner leads 7B, 7B located on both sides of the upper inner lead, and bonding areas 8A of the upper inner leads 7A being positioned radially outwards with respect to bonding areas 8B of the lower inner leads 7B, whereby the pitch between inner leads can be reduced to half, and the number of pins can be increased under the condition that the size of a resin sealing body 24 is fixed. Further, wire bonding can be done properly because a reaction force induced at the time of wire bonding for the upper inner leads 7A is borne at the overlapped portions of the lower inner leads 7B, 7B.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.