Selectable timing delay system
US5382850A · kind A · utility
5Cited by
10References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1992 |
| Grant date | Jan 17, 1995 |
| Priority date | — |
| Expiry date | Sep 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A selectable timing delay system which provides for delaying an input signal a specified length of time within a specified tolerance wherein the range and resolution of the selectable timing delay system are so specified that the selected delay within the selected tolerance is obtainable regardless of the relative speed of the integrated circuit chips used in forming the selectable timing delay system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.