Protective system for insertion/extraction of PC boards in a powered-up environment
US5384492A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1992 |
| Grant date | Jan 24, 1995 |
| Priority date | — |
| Expiry date | Nov 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/004
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for handling the connection/disconnection transition period of a printed circuit board to an actively empowered backplane which eliminates damaging surge currents and glitches by the use of temporarily functioning field effect transistor circuits which gradiently handle the current loads during the transition period. A set of specifically sized and predetermined lengths of connecting pins on the backplane insures that a programmed sequence of power connection and/or disconnection will occur which permits a group of field effect transistors to gradiently carry the changing current loads that occur during the insertion of the printed circuit board into the backplane. Likewise, during extraction of the printed circuit board from the backplane, the group of FETs (Field Effect Transistors) will carry and buffer the changing current loads from de-stabilizing the power supply source unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.