Sample and hold circuit
US5384496A · kind A · utility
10Cited by
5References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1993 |
| Grant date | Jan 24, 1995 |
| Priority date | — |
| Expiry date | Jul 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0209
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit is arranged to have a common input bus line and a plurality of combinations of analog switches and capacitors connected to the command input bus line. The sample and hold circuit includes as features a signal feeding unit for sequentially feeding a sampling control signal to the analog switches and a preventing unit for preventing the plurality of analog switches from being made conductive at one time because of the delay of the sampling control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.