Packet assembler
US5384770A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 1992 |
| Grant date | Jan 24, 1995 |
| Priority date | — |
| Expiry date | May 8, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/56
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for reducing latency delay associated with converting asynchronous, serial digital data to packet data. The number of data characters received before a time-out occurs are counted; the last character received before a time-out occurs is recognized; or the number of data characters transmitted before a signal is received from the destination terminal are counted. The information thus gathered is used to predict the occurrence of future latency delay. Data packets are transmitted immediately upon the subsequent receipt of a number of data characters equal to the number of data characters received before the time-out occurred; receipt of a character identical to the last character received before a time-out; or receipt of a number of data characters equal to the number of data characters transmitted before another signal is received from the destination terminal, respectively. By transmitting immediately when a latency delay is expected, the latency delay is completely avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.