Method for manufacturing vertical MOS transistors

US5385852A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Klaus-Guenter Oppermann · Holzkirchen, DE
• Wolfgang Roesner · Austin, US
• Franz Hofmann · Munich, DE

Key dates

• Filing date: Dec 9, 1993
• Grant date: Jan 31, 1995
• Expiry date: Dec 9, 2013

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/126

Abstract

For manufacturing vertical MOS transistors, doped regions for a drain (11), well (3), and source (4) are formed in a vertical sequence in a substrate (1). Using a Si.sub.3 N.sub.4 mask (5), trenches (6) are etched perpendicular to the surface of the substrate (1). The trenches isolate the source (4) and well (3) structure, and are filled with doped polysilicon and are closed in an upper region with an insulation structure (8) in self-aligned fashion on the basis of local oxidation. The insulation structure (8) projects laterally beyond the trenches (6). Using the insulation structure (8) as an etching mask, via contact holes (9), that are provided with a metallization for contacting the source (4) and the well (3), are opened down into the well (3) between neighboring trenches (6).