Semiconductor memory device
US5386131A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 1992 |
| Grant date | Jan 31, 1995 |
| Priority date | — |
| Expiry date | Sep 14, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
A DRAM having memory cells each consisting of a MOS transistor and a trench-stack capacitor built at a p-type silicon substrate. The MOS transistor comprises a source region made of the first diffused n.sup.- layer, and a drain region composed of the first diffused n.sup.- layer and the first diffused n.sup.+ layer self-aligned with respect to a bit contact hole. At the surface of the p-type silicon substrate is formed a trench penetrating through the source region near the gate electrode of the MOS transistor working also as a word line. The capacitor is built to extend deep into a U-shaped section. The second diffused n.sup.- layer is formed at the the trench sidewall surface of the p-type silicon substrate, and the second insulating film is formed over the sidewall of the trench. The second diffused n.sup.+ layer is formed at the trench bottom surface of the p-type silicon substrate. The bottom face of the trench functions as a node contact hole of the memory cell. The storage node electrode of the trench-stacked capacitor is electrically connected through the node contact hole, the second diffused n.sup.+ layer and the second diffused n.sup.- layer to the source region. The str…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.