Data processing system for generating symmetrical range of addresses of instructing-address-value with the use of inverting sign value
US5386534A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1992 |
| Grant date | Jan 31, 1995 |
| Priority date | — |
| Expiry date | Oct 27, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. An instruction specifying an operation to be performed, a pointer register (58, 60), and an offset value is provided to an execution unit (14). The pointer register (58, 60) stores a first address value and the offset value has a sign and a magnitude. An arithmetic logic unit, ALU, (52) inverts the sign of the offset value to provide an inverted sign value. A plurality of adders (100, 102, 104, 106, and 108) adds the offset value, the first address value, and the inverted sign value to generate an offset sum. A positive offset value is increased by one to generate a symmetric power of two offset range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.