Heterojunction bipolar transistors with sloped regions
US5387808A · kind A · utility
7Cited by
1References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1993 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Jan 21, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/05
Abstract
The present invention is directed toward a heterojunction bipolar transistor integrated circuit in which the collector layers of two heterojunction bipolar transistors are provided on a semi-insulating substrate. The collector layers have at least one surface that is sloped relative to the substrate. Base layers are provided on the sloped portions a common emitter layer is provided in contact with the base layers. Alternatively, the common emitter layer is provided on the substrate and etched to form to sloped surface thereon. Base and collector layers are then formed on the sloped surfaces of the common emitter layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.