Error signal isolator circuit
US5387822A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1992 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Nov 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/33523
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An error signal isolator circuit for conveying an error signal across an electrical isolation boundary such as an external pulse transformer employs a level shifting process whereby a controllable voltage is measured with respect to a reference voltage and, with any gain implemented in the process, is level shifted upward such that the higher potential is referenced to a supply voltage and the lower potential is used dynamically to control the magnitude of voltage conveyed in a pulse amplitude modulation (PAM) process. In the PAM process, an ON pulse is terminated by monitoring when a PAM current has increased to a predetermined and controllable level. An ON pulse is initiated by monitoring when the voltage across a clamp diode has decayed below its normal forward bias level, indicating a commensurate decay in PAM current, following termination of the previous ON pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.