Semiconductor integrated circuit having logic gates
US5387827A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1991 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Jan 22, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.