Receiver with digital tuning and method therefor
US5387913A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1993 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Nov 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J5/0272
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A receiver (20) digitally tunes a radio frequency (RF) signal at the same time that it mixes the RF signal to a frequency suitable for demodulation and channel separation. A clock frequency divider (35) receives a reference clock signal, and divides the reference clock signal to provide a divided signal at a predetermined frequency, such as 20 kHz for AM stereo. A clock frequency multiplier (36) receives the divided signal and a digital tuning input signal, and provides an analog tuning signal at a multiple of the divided signal as determined by the digital tuning input signal. An analog multiplier (31) then mixes the RF signal with the analog tuning signal. An analog-to-digital converter (ADC) (32) receives an output of the analog multiplier (31), and is clocked by the reference clock signal to eliminate any clock phase error. A digital demodulator (38) then demodulates and further processes an output of the ADC (32).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.