Semiconductor memory cell
US5388067A · kind A · utility
10Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1994 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Apr 1, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flip-flop is composed of inverters including first and second MISFETs each comprising a TFT or an SOI transistor. A third MISFET, which comprises a TFT or an SOI transistor, has a gate connected to a write selecting signal line, and is connected between the output terminal of one of the inverters and a write/read signal line. A fourth MISFET has a gate connected to the gate of the other inverter. A fifth MISFET has a drain and a source connected to the write/read signal line and the drain of the fourth MISFET, and a gate connected to a read selecting signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.