Memory subsystem command input queue having status locations for resolving conflicts

US5388222A · kind A · utility

Assignee

• Digital Equipment Corporation · US

Inventors

• Lawrence A. P. Chisvin · Sudbury, US
• John K. Grooms · Webster, US
• Joseph F. Rantala · Worcester, US
• David W. Hartwell · Lancaster, US

Key dates

• Filing date: Mar 28, 1994
• Grant date: Feb 7, 1995
• Expiry date: Mar 28, 2014

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0806
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Methodology and circuitry for managing read and write commands from nodes to a shared memory resource on a common data bus, including nodes with write-back caches, nodes with write-through caches and nodes without caches.