DRAM chip and decoding arrangement and method for cache fills
US5388240A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1991 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Aug 29, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data mechanism having a random access memory (RAM) which has a plurality of groups of memory chips, each group being divisible into two equally sized chip sets. Each group of memory chips is addressed by a first address and each individual memory chip is addressed by a second address. The random access memory contains stored data. A cache, connected to the RAM, stores a portion of data stored in the RAM and is accessed by a cache address for separately reading requested data therefrom. The cache provides a cache miss signal when it does not contain the requested data. A CPU, connected to the cache and the RAM, receives the cache miss signal and provides responsive thereto, a starting address to the random access memory for starting a block transfer from the random access memory to the cache in two shots. The starting address includes the first address and the second address. The starting address identifies the group and individual chip within the group which contains the first bit which, when attempted to be read from the cache, caused the cache miss signal. A decoder, connected to the CPU and the random access memory, receives the starting address from the CPU and enables a firs…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.