Vertical and lateral isolation for a semiconductor device
US5389569A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1992 |
| Grant date | Feb 14, 1995 |
| Priority date | — |
| Expiry date | Mar 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76289
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for making a power device (54) and a small signal device (52) on a bonded silicon substrate (41). A first silicon substrate (10) provided. A first surface (17) is etched to form a plurality of cavities (11) with a depth (13). A dielectric layer (14) is created on the first surface (17), wherein the dielectric layer (14) is created with a thickness less than or equal to the depth of the plurality of cavities. The dielectric layer (14) is patterned so that a plurality of islands (22) of dielectric remain in the cavities. A second silicon substrate (42) is provided. The first and the second silicon substrates (10, 42) are bonded together in such a manner that the islands (22) are buried. A predetermined portion of the first silicon substrate (10) is removed, thereby creating a surface that is suitable for semiconductor device fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.