Field effect transistor
US5389807A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1993 |
| Grant date | Feb 14, 1995 |
| Priority date | — |
| Expiry date | Aug 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/221
Abstract
It is an object of the present invention to provide a dual-gate type MESFET having a high drain breakdown voltage and excellent high-frequency characteristics. A semiconductor substrate used in the present invention is obtained by sequentially forming a non-doped buffer layer 2, a thin first pulse-doped layer 3 having a high impurity concentration, and a cap layer 7 on an underlying semiconductor substrate 1 by epitaxial growth. The cap layer 7 has a thin second pulse-doped layer 5 having a high impurity concentration sandwiched between non-doped layers 4 and 6. The thickness and impurity concentration of the second pulse-doped layer 5 are set such that the second pulse-doped layer 5 is depleted by a surface depletion layer caused by the interface state of the cap layer surface, and the surface depletion layer does not extend to the first pulse-doped layer 3. A source electrode 13, a drain electrode 16, and first and second gate electrodes 14 and 15 are formed on the semiconductor substrate surface. High-impurity-concentration ion implantation regions 10, 11, and 12 are formed at a source electrode formation region, a drain electrode formation region, and a region between the first…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.