Clock generation
US5389830A · kind A · utility
12Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1992 |
| Grant date | Feb 14, 1995 |
| Priority date | — |
| Expiry date | Aug 24, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is described clock generation circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control circuitry common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.