Devices, systems and methods for implementing a Kanerva memory
US5390139A · kind A · utility
9Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 1993 |
| Grant date | Feb 14, 1995 |
| Priority date | — |
| Expiry date | May 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90339
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is provided for identifying at least one active address from ones of the possible addresses stored in first memory 20 as a function of the actual address stored in second memory 22.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.