Static random access memory device having thin film transistor loads

US5391894A · kind A · utility

Assignee

• FUJITSU LIMITED · JP

Inventors

• Kazuo Itabashi · Kawasaki, JP
• Taiji Ema · Inabe, JP

Key dates

• Filing date: Jul 13, 1993
• Grant date: Feb 21, 1995
• Expiry date: Jul 13, 2013

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/903

Abstract

A semiconductor memory device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, and first and second word lines extending generally parallel to each other along a predetermined direction and respectively coupled to gate electrodes of the first and second transfer transistors. Each of the first and second thin film transistor loads include first and second impurity regions which sandwich a channel region formed by a semiconductor layer provided on the semiconductor substrate, and a gate electrode formed by confronting conductor layers and isolated from the channel region. The first driver transistor includes a drain which is coupled to one of the impurity regions of the first thin film transistor load and to a gate of the second driver transistor via a first connection region, and the second driver transistor includes a drain which is coupled to one of the impurity regions of the second thin film transistor load and to a gate of the first driver transistor via a second connection region. The first and second c…