Decoder circuitry with balanced propagation delay and minimized input capacitance
US5391941A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Sep 23, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit implementing a logic NAND function with respect to a first input signal and a second input signal is described. First and second P-channel transistors are coupled in parallel to a power supply and an output node. Each of the first and second P-channel transistors receives the respective one of the first and second input signals. A first circuit branch has a first and a second N-channel transistor. The first N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the second N-channel transistor. The second N-channel transistor has a second end coupled to ground. The first N-channel transistor receives the first input signal and the second N-channel transistor receives the second input signal. A second circuit branch has a third and a fourth N-channel transistor. The third N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the fourth N-channel transistor. The fourth N-channel transistor has a second end coupled to ground. The third N-channel transistor receives the second input signal and the fourth N-channel transistor receives the first input signal such that t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.