Gate array cell with predefined connection patterns
US5391943A · kind A · utility
6Cited by
3References
33Claims
0Family size
Inventors
Key dates
| Filing date | Jan 10, 1994 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Jan 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1735
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10 and a plurality of P-channel transistors 12. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional N-channel (14) and P-channel (70, 72) transistors are included in the base cell at least some of which are larger in size than those in the plurality of N-channel transistors 10 or the plurality of P-channel transistors 12. These larger size transistors are used as output drivers to send the logical output signal of the cell to another cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.