Circuit and method for providing phase synchronization of ECL and TTL/CMOS signals
US5391945A · kind A · utility
1Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Sep 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00323
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method for providing phase synchronization between an ECL output signal and a TTL or CMOS output signal has been provided. The circuit includes phase locked loops (20, 24) to make the difference of delays through an ECL-TTL/CMOS translation path with that of a straight ECL path irrelevant. As a result, in order to achieve phase synchronization between an ECL signal and a TTL/CMOS signal, one only needs to match the propagation delay of a delay component (22) to that of a TTL/CMOS-ECL translator (26) as opposed to a delay component and an ECL-TTL/CMOS translator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.