Procedure to minimize total power of a logic network subject to timing constraints
US5392221A · kind A · utility
33Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1991 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Jun 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for minimizing the total power of a logic network subject to timing constraints. The method describes a procedure to assign power and/or delay to each circuit in a logic network such that the total power is minimized and the arrival time requirement at the outputs of the logic network is met. A subset of circuits in the logic network are powered up and powered down in repeated succession in order to minimize the total power of the logic network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.