Burst-mode DRAM
US5392239A · kind A · utility
153Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | May 6, 2013 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC07K2319/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequential column addresses within a given row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.