Configurable spare memory chips
US5392292A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Nov 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory reconfiguration system dynamically configures spare chips into memory during system operation by shifting data around defective chips. The shifting of data around an entire memory chip allows the system to correct bit, addressing, and control errors or faults within the chip. When the system detects an error, or otherwise initiates a memory reconfiguration, it transmits a configuration code to shift registers for a memory write driver. The shift registers, in response to the configuration code, shift write data so that the data is effectively shifted around a particular memory chip and into a spare memory chip. The system selectively transmits the configuration code to shift registers for a memory read driver. Therefore, the system independently shifts data written to the memory inputs and data read from the memory outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.