Triple orthogonally interleaed error correction system
US5392299A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 15, 1992 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Jan 15, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/31
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The detection and correction of errors in digital data transmitted by or stored in a media channel is provided by processing the data through a triple orthogonally interleaved error correction system. On the transmit/store side of the system, the data is encoded three times prior to placement in the media channel with two different interleaving steps performed between the encoding steps. The first interleave is an orthogonal row shuffling interleave that provides enhanced protection against burst errors. On the receive/play back side, the data is decoded and deinterleaved, with included errors detected and corrected to enable recovery of the original data. To enhance the error correction, a circuit is used for generating a symbol accurate error flag identifying symbols containing errors thereby allowing the error correcting decoders to focus on and correct the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.